Audible noise is an undesired physical manifestation caused by a motherboard flexing at a frequency in the audible range, in response to voltage changes across capacitors, especially ceramic capacitors, on the motherboard due to the inherent Piezoelectric phenomenon of the capacitor.
One conventional approach to eliminate the audible noise is to control the voltage change of the voltage identification (VID) signal sent from a master device (e.g., CPU) to a voltage regulator when the master device is transited from the present state to a lower power state. The VID is either changed to a VID value higher than the target value associated with the lower power state to reduce the voltage change, or set to have the same value as that of the present state so that no voltage change presents. Power loss is a big issue in such an approach as the VID is always kept at a higher VID value even when the condition creating the audible noise subsides.
As another conventional approach to eliminate the audible noise, Intel Corporation provides the users an ability to slow down the ramp rates of the voltage change. However, this does not always solve the issue, and can reduce or eliminate the duration that the platform can go into the lower power state.
An approach at least addressing the above-mentioned issue is thus desired.